Monday, January 28, 2013

CST at HSPICE SIG 2013

HSPICE is the industry “gold standard” for accurate circuit simulation, offering foundry-certified semiconductor device models and state-of-the-art simulation and analysis algorithms. The Synopsys HSPICE special interest group (SIG) is an active community for all HSPICE users and design engineers who want to stay connected with the latest developments in the field of circuit simulation.

CST is a partner in Synopsys’ HSPICE Integrator Program (HIP) and CST STUDIO SUITE® can be easily integrated with HSPICE. CST MICROWAVE STUDIO®, CST PCB STUDIO® and CST DESIGN STUDIO™ can all extract the broadband network parameters of circuits and components from both 2D and 3D models for use in HSPICE simulations. Using CST STUDIO SUITE® and HSPICE together allows designers to incorporate arbitrary components such as connectors and sections of PCB nets into fast, accurate circuit simulations.

HSPICE SIG 2013 takes place during DesignCon 2013 on Tuesday, January 29 in the Santa Clara Marriott Hotel, 2700 Mission College Boulevard and starts at 6 PM right after show close. The event is divided into two parts, beginning with registration and cocktails in the hotel’s luxurious Hall of Cities Ballroom. As a HIP partner for many years, we will be happy to discuss our capabilities with you there. At 7:30 PM, dinner and technical presentations start in the Grand Ballroom. The scheduled dinner presentations are:
  • Electrical Modeling of Through Silicon Vias Using HSPICE – Micron
  • Using IBIS-AMI Models Effectively in HSPICE – Altera
  • Top-Down Circuit Design Using HSPICE – AMD
  • HSPICE 2013—When Was Your Last Test Drive? – Synopsys R&D
We believe that this will be a great event for circuit designers and engineers, and hope to see you there.

CST at DesignCon 2013

DesignCon is perhaps the premier conference for the chip design industry, where the semiconductor and electronic design engineering community gathers every year for intensive technical learning and networking. DesignCon 2013 takes place at the Santa Clara Convention Center from Monday, January 28 to Thursday, January 31, with the exhibition floor open on Tuesday and Wednesday afternoon.

We have been attending, exhibiting and contributing to DesignCon for many years, and consider it to be one of the most influential shows on CST’s tradeshow calendar. As well as exhibiting at DesignCon 2013 at Booth #403, we are once again actively contributing to the program with a series of presentations and training sessions:

·         Modeling and Optimization of High-Speed Interconnects for Signal and Power Integrity
Monday, 28 January, 9.00 AM to 12:00 AM.
Antonio Ciccomancini Scogna, CST; Mauro Lai, Intel; Madhumitha Seshadhri, Intel; Darryl Kostka, CST and Jonathan Casanova, Intel.

·         Interactions Between Power Planes and Power Planes to Traces in Power-Integrity Issues
Tuesday, 29 January, 11.05 AM to 11.45 AM.
Richard Sjiariel, CST and Joachim Held, Siemens.

·         Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB
Tuesday, 29 January, 3.45 PM to 5.00 PM.
Antonio Ciccomancini Scogna, Darryl Kostka, Martin Schauer and Richard Sjiariel.

This session is free and open to all attendees.

A detailed description of CST related events at DesignCon 2013 is shown below. During the exhibition we will be at Booth #403 (a map of the exhibition hall is available here). We hope to see you there!

DesignCon 2013. Conference: Jan. 28 - 31, Expo: Jan. 29 & 30