Monday, January 28, 2013

CST at DesignCon 2013

DesignCon is perhaps the premier conference for the chip design industry, where the semiconductor and electronic design engineering community gathers every year for intensive technical learning and networking. DesignCon 2013 takes place at the Santa Clara Convention Center from Monday, January 28 to Thursday, January 31, with the exhibition floor open on Tuesday and Wednesday afternoon.

We have been attending, exhibiting and contributing to DesignCon for many years, and consider it to be one of the most influential shows on CST’s tradeshow calendar. As well as exhibiting at DesignCon 2013 at Booth #403, we are once again actively contributing to the program with a series of presentations and training sessions:

·         Modeling and Optimization of High-Speed Interconnects for Signal and Power Integrity
Monday, 28 January, 9.00 AM to 12:00 AM.
Antonio Ciccomancini Scogna, CST; Mauro Lai, Intel; Madhumitha Seshadhri, Intel; Darryl Kostka, CST and Jonathan Casanova, Intel.

·         Interactions Between Power Planes and Power Planes to Traces in Power-Integrity Issues
Tuesday, 29 January, 11.05 AM to 11.45 AM.
Richard Sjiariel, CST and Joachim Held, Siemens.

·         Advances in 3D SI Simulations of Interconnects for Chip/Package/PCB
Tuesday, 29 January, 3.45 PM to 5.00 PM.
Antonio Ciccomancini Scogna, Darryl Kostka, Martin Schauer and Richard Sjiariel.

This session is free and open to all attendees.

A detailed description of CST related events at DesignCon 2013 is shown below. During the exhibition we will be at Booth #403 (a map of the exhibition hall is available here). We hope to see you there!

DesignCon 2013. Conference: Jan. 28 - 31, Expo: Jan. 29 & 30







Monday, January 28

9.00 AM, Ballroom D.
Duration: 3 hours
Presenters: Antonio Ciccomancini Scogna, CST; Mauro Lai, Intel; Madhumitha Seshadhri, Intel; Darryl Kostka, CST and Jonathan Casanova, Intel
At very high speed, passive channels pose significant challenges for serial link transmission. This tutorial will cover the different design challenges in chips, packages, and PCBs, as well as the interactions between them. The goal of the tutorial is to provide modeling and design guidelines to signal integrity (SI) engineers dealing with the design of high-speed interconnects in electronic PCBs and packages. Transmission-line theory will be revisited in order to explain how to take into account such important phenomena as surface roughness, the glass weave effect and proper material models. Modeling of discontinuities (both planar and vertical) will be discussed in depth, along with possible solutions to mitigate their effect and improve the SI. Alternative design solutions to reduce the coupling between signal lines and power planes (caused by uncontrolled return current) are presented.

11.05 AM, Ballroom G.
Duration: 40 minutes
Presenters: Richard Sjiariel, CST and Joachim Held, Siemens
The costs of manufacturing mean that engineers are demanding PCBs with low layer counts and high packing densities, yet at the same time, the number of supply voltages needed by PCB components is rising. Balancing these two requirements leads to PCBs with a lot of power planes that are very close together and not separated by adjacent ground layers. Exacerbating matters, many stackups use traces between the power and ground planes. This causes interactions due to RF energy transfer between traces and supply systems as well as between the supply systems themselves. These phenomena can be observed in terms of noise transfer from one system to another and the coupling of resonances between the different systems – in other words, one supply system exhibits additional resonance frequencies not seen when simulated alone. This session compares different types of systems and works out, by simulation, the kind of interaction each one experiences. Various cases are identified and guidelines are provided for cases where other traces or power planes should be included in the power integrity (PI) simulation. 

3.45 PM, Mission City Ballroom M1.
Duration: 1 hour, 15 minutes
Presenters: Antonio Ciccomancini Scogna, Darryl Kostka, Martin Schauer and Richard Sjiariel
Memory interfaces have single-ended data rates in the 1 GHz-plus range, and serial links run upwards of 20 Gbs. A precise analysis of each of these signals is required at silicon, package and board level and the optimization must be done in a global context. The goal of this training section is to provide a comprehensive understanding of the physical phenomena involved in the design of high speed interconnects, bridging signal integrity (SI) and power integrity (PI) as well as, to some extent, electromagnetic interference (EMI). This training session presents efficient EM workflows for both SI and PI analysis of chip/package/board systems as well as co-design approaches, pre- and post-layout analysis of PCBs, and new developments in the Via Wizard for modeling of multi-via structures. The sessions will outline techniques for modeling and characterizing TSVs and interposers for 3D system integration, and propose a global methodology which combines 3D electromagnetic analysis for PCBs and packages with chip power-switching macro-modeling. The speakers will discuss the difference between the segmentation approach (where silicon, package and PCB are analyzed separately and then combined with standard cascading technique) and the integrated or global approach (where chip, package and PCB are analyzed as single entity in a co-simulation mode), and suggest guidelines for where and when each approach is most appropriate. Session sub-topics and speakers below:

·         Efficient Pre and Post Layout Analysis of PCBs – Richard Sjiariel

·         CST Via Wizard: New Developments – Martin Schauer

·         TSV and Interposers for 3D Systems Integration – Darryl Kostka

·         Modeling and Characterization of Electronic Packaging Structures – Antonio Ciccomancini
Training sessions are sponsored; they are free and open to all attendees.

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