Monday, February 4, 2013

Finding Solutions at DesignCon

CST at DesignCon 2013
We're back from DesignCon 2013 and are excited to see that interest in simulation has soared this year. There was a record crowd of engineers at our booth all looking for solutions to complex signal and power integrity issues or EMC related concerns. CST’s breadth of technology seemed to be of great interest and now we look forward to many follow-ups over the next few weeks to help companies get to the bottom of some really tough design problems.

As part of the conference, CST sponsored a 75 minute tutorial session looking at advances in 3D SI simulation of interconnects across chip, package and board. This attracted a capacity audience of around 150 people. In addition, CST was involved in some of the main conference tracks including a presentation together with Siemens looking at Power-Integrity Issues between power planes and power planes & traces and a presentation with Intel on Modeling and Optimization of High-Speed Interconnects for Signal and Power Integrity.

DesignCon is all about finding solutions for increasingly fast data through various channels. CST’s advanced EDA import filters, powerful time-domain and PI solvers, and advanced interface and workflow solutions as well as high performance computing options make traditionally difficult simulations or optimizations in multi-way interconnect, multilayer stack ups, complex backplanes, PCB/package EMI, enclosures, or even the complete chip/package/board channel light work.

Usability and workflow take a big step forward in version 2013 of CST STUDIO SUITE®, shipping in the Spring - stay tuned!

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